library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type state_type is (s1,s2,s3,s4);
signal current_s,next_s: state_type;
begin
process (clk,clr)
begin
if (clr='1') then
current_s <= s1; --default state after reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;