process (current_s,a,b)
begin
case current_s is
when s1 => --when current state is "s1"
y2 <= '0';
y1 <= '0';
if(a ='0' and b='0') then
next_s <= s1; -- nothing happens - stay in the first state
elsif (a ='1' and b='0') then
next_s <= s2; -- first combination a=1, b=0 then go to the
next state
else
next_s <= s4; -- bad input combination -> alarm stage
end if;
---------------
when s2 => --when current state is "s2"
y1 <= --insert the proper value
y2 <= --insert the proper value
if (a =--insert the proper value and b=--insert the proper
value) then
next_s <= --insert the proper state;
elsif(a ='1' and b='1') then –- final combination for open
lock
next_s <= --insert the proper value;-- lock is opened in the
next state
--y1 <= '1';--if uncomment, lock is open in this state
after right combination
--y2 <= '0';
else
next_s <= --insert the proper state;
end if;
------------------
when s3 => --when current state is "s3", open state
-- Insert vhdl code for state s3
----------------------
when s4 => --when current state is "s4", alarm state
y1 <= '0';
y2 <= '1';
next_s <= s4; -- stay in the alarm state, the alarm can be
turned off by reset clr
end case;
end process;
end Behavioral;